In association with lowering in power consumption and increase in functionality and in speed of electronics equipment, lower power consumption or higher speed operation is demanded in semiconductor devices accompanied by such equipment. In order to satisfy such demands, low ON resistance of transistors is required in semiconductor devices generally used in DC-DC converters of electronics equipment. As one method for reducing the ON resistance of transistors, the density of the transistors arranged per unit area may be increased.
Specifically, a method has been proposed in which a gate electrode of a semiconductor device is arranged vertically (along a direction perpendicular to the principal plane of the substrate). As a semiconductor device employing this method, there is vertical gate semiconductor device. In the vertical semiconductor device, the gate electrode is vertically arranged and the source region is formed so as to face the upper part of the gate electrode. Also, the drain region is formed so as to face the bottom part of the gate electrode.
In the vertical gate semiconductor device, of which gate electrode is arranged vertically, the uppermost face of the vertical gate electrode and the surface of the silicon region where the source region is formed is almost on a level. Therefore, in order to prevent conduction between the vertical gate electrode and the source region or the body contact region, it is necessary to cover the upper part of the vertical gate electrode with, for example, a convex insulating film when the source region and the body contact region are connected to the common electrode.
As a prior art for solving this problem, there has been proposed a technique disclosed in Japanese Patent Application Laid Open Publication No. 2000-252468A. In this reference, the above problem is solved in such a manner that in a plurality of vertical gate semiconductor devices arranged in parallel with each other, the uppermost face of each gate electrode is concaved from the level of the surface of the silicon region where the source region is formed and an insulating film is filled in the concave part above the vertical gate electrode.
A conventional vertical gate semiconductor device disclosed in Japanese Patent Publication No. 2662217B or Japanese Patent Application Laid Open Publication No. 2000-252468A will be described below with reference to drawings.
FIG. 1A is a view showing a structure in section of a conventional vertical gate semiconductor device, specifically, a N-channel vertical gate DMOS (Double Diffused Metal Oxide Semiconductor) transistor.
As shown in FIG. 1A, an epitaxial layer 1810 is formed on a silicon substrate 1800, which is a N+-type semiconductor substrate with N-type (first conductivity type) impurity doped, by an epitaxial growth method. The epitaxial layer 1810 includes a N-type drain region 1811, a P-type body region 1812 formed on the drain region 1811, a N+-type source region 1813 formed on the body region 1812, and a P+-type body contact region 1814 which is formed adjacent to the source region 1813 and has an impurity concentration higher than that of the body region 1812. In the epitaxial layer 1810, a trench passing through the source region 1813 and the body region 1812 and extending to the upper part of the drain region 1811 is formed and a vertical gate electrode 1820 is buried in the trench. The level of the uppermost face of the vertical gate electrode 1820 is lower than the level of the surface of the epitaxial layer 1810 where the source region 1813 is formed. An insulating film 1830 is filled over the vertical gate electrode 1820 in the trench. Further, an insulating material 1840 serving as a gate insulating film intervenes between the vertical gate electrode 1820 and the respective faces of the drain region 1811 and the body region 1812 each serving as a vertical face of the trench. In addition, a common electrode 1850 to which the source region 1813 and the body contact region 1814 are commonly connected is formed on the epitaxial layer 1810.
FIG. 1B is a plan view showing a MOSFETs array in which cells are arranged in arrays, with the use of the MOSFET shown in FIG. 1A as one cell (one unit). Wherein, FIG. 1A is a section taken along a line A–A′ of FIG. 1B. In addition, the members other than the vertical gate electrode 1820, the source region 1813 and the body contact region 1814 are not shown in FIG. 1B.
As described above, the epitaxial layer (semiconductor layer) 1810 of the conventional vertical gate semiconductor device shown in FIGS. 1A and 1B includes the N-type drain region 1811, the P-type body region 1812 formed on the drain region 1811, and the N+-type source region 1813 and the P+-type body contact region 1814 which are formed on the body region 1812 so as to be adjacent with each other. Each surface of the source region 1813 and the body contact region 1814 serves as the surface of the semiconductor layer 1810. Further, the upper part of the vertical gate electrode 1820 faces the source region 1813 and the bottom part of the vertical gate electrode 1820 faces the drain region 1811.
In a vertical gate semiconductor device having the above construction, the insulating film 1830 prevents conduction between the vertical gate electrode 1820 and the source region 1813 or the body contact region 1814. Accordingly, a step of covering the upper face of the vertical gate electrode 1820 with an insulating film, which has been performed when the source region 1813 and the body contact region 1814 are connected in common to the common electrode, can be omitted.
Moreover, since the uppermost face of the insulating film 1830 and the surface of the silicon region (semiconductor layer 1810) where the source region 1813 is formed are on a level, the subsequent masking step can be performed on a plane surface, thereby facilitating the fabrication of the vertical gate semiconductor device.
FIGS. 2A and 2B are sections each showing a construction of another conventional vertical gate semiconductor device, specifically, a N-channel vertical gate DMOS transistor disclosed in Japanese Patent Application Laid Open Publication No. 2000-252468A. Wherein, FIG. 2A is a section showing a first region functioning as a MOS transistor and FIG. 2B is a section showing a second region for electrical contact with the body region of the transistor.
As shown in FIG. 2A, in the first region, a N-type drain region 2811 is formed on a silicon substrate 2800, which is a N+-type semiconductor substrate with a N-type (first conductivity type) impurity doped. A P-type body region 2812 is formed on the drain region 2811 and a N+-type source region 2813 is formed on the body region 2812. Through the source region 2813 and the body region 2812, a trench extending to the upper part of the drain region 2811 is formed and a vertical gate electrode 2820 is buried in the trench. The level of the uppermost face of the vertical gate electrode 2820 is lower than that of the surface of the semiconductor layer where the source region 2813 is formed. An insulating film 2830 is filled over the upper part of the vertical gate electrode 2820 in the trench. Also, an insulating material 2840 serving as a gate insulating film intervenes between the vertical gate electrode 2820 and the respective faces of the drain region 2811 and the body region 2812 each serving as a vertical wall face of the trench. In addition, a common electrode 2850 to be connected to the source region 2813 is formed on the source region 2813.
On the other hand, as shown in FIG. 2B, the second region has the same sectional construction as in the first region, except that a P+-type body contact region 2814 is formed in lieu to the source region 2813 shown in FIG. 2A.
FIG. 2C is a plan view showing the MOSFETs array in which the first region shown in FIG. 2A and the second region shown in FIG. 2B are alternately arranged in stripes along a direction along which the vertical gate electrode 2820, namely, the gate trench extends. Wherein, the members other than the vertical gate electrode 2820, the source region 2813 and the body contact region 2814 are not shown in FIG. 2C.
As shown in FIG. 2C, the source region 2813 and the body contact region 2814 are alternately arranged along the respective gate electrodes 2820 (i.e., gate trenches), so that the plural arrays in stripes is formed. The respective arrays are arranged adjacent to the respective gate trenches and are separated from one another by the respective gate trenches. Further, referring to the vertical dimension (dimension along which the gate trenches extend) in the arrays arranged beside the gate trenches, the source region 2813 has a relatively long dimension and the body contact region 2814 has a relatively short dimension, as shown in FIG. 2C. In other words, the first region functioning as a transistor has a larger area than that of the second region functioning as a body contact.
With the latter conventional vertical gate semiconductor device having the striped layout shown in FIG. 2A through FIG. 2C, the intervals between the gate trenches can be set narrower than that in the conventional MOSFETs array having the cellular layout shown in FIGS. 1A and 1B.
In order to ensure the contact area between the source region and the electrode (common electrode) in such conventional MOSFETs array in the cellular layout, for example, Japanese Patent Application Laid Open Publication No. 2001-085685A or Japanese Patent Application Laid Open Publication No. 11-103052A discloses a technique of forming an insulating film over the gate electrode in the gate trench so that the level of the uppermost face of the insulating film is lower than the level of the surface of the semiconductor layer where the source region is formed. In this technique, the source region and the common electrode can be in contact partially with each other in the respective parts of the gate trench wall face and the surface of the semiconductor layer.
However, in such a conventional vertical gate semiconductor device having the aforementioned cellular layout, the contact resistance of the source region is increased in association with size reduction of the device for miniaturization. In detail, if a distance between the adjacent trench gate electrodes is narrowed in association with the size reduction of the vertical gate semiconductor device, the source region is also narrowed accordingly. For example, in a vertical gate semiconductor device in which vertical gates each having a width of 0.25 μm are arranged at intervals of 0.25 μm, if the intervals between the vertical gate electrodes are shortened 0.1 μm, the width of the vertical gate electrodes cannot be shortened when taking account of the resistance of polysilicon. Therefore, the intervals between the vertical gate electrodes must be narrowed to 0.15 μm necessarily, with a result of extremely small source region formed therebetween. Hence, the contact area between the common electrode and the source region becomes small, resulting in increased contact resistance of the source region.
It is noted that a smaller contact area between the common electrode and the body contact region increases the contact area between the common electrode and the source region because the layout area where the body contact region is arranged and the layout area where the source region is arranged are in a relationship of trade-off. However, such a smaller contact area between the common electrode and the body contact region leads to insufficient grounding of the body region and invites a parasite bipolar transistor to operate.
On the other hand, in a conventional vertical gate semiconductor device having the aforementioned striped layout, the intervals between adjacent trench gate electrodes are narrowed in association with size reduction of the device for miniaturization, and the source region is narrowed accordingly. In its turn, the contact area between the common electrode and the source region becomes small, resulting in increased contact resistance of the source region.